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Verilog questions

2to4 decoder
1to4 demux
4to1 mux
full adder
half adder
half subtractor
4 bit up/doen counter
siso
full subtractor
sipo
odd parity
even parity
xs3 to bcd
bcd to xs3
binary to gray
gray to binary
4input universal logic gates
octal to binary
8to 1 mux

// Design Name : full_subtracter_gates
3 // File Name : full_subtracter_gates.v
4 // Function : Full Subtracter Using Gates
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module full_subtracter_gates(x,y,z,difference,borrow);
8 input x,y,z;
9 output difference,borrow;
10
11 wire inv_x,borrow1,borrow2,borrow3;
12
13 not (inv_x,x);
14 and U_borrow1 (borrow1,inv_x,y),
15 U_borrow2 (borrow2,inv_x,z),
16 U_borrow3 (borrow3,y,z);
17
18 xor U_diff (difference,borrow1,borrow2,borrows);
19
20 endmodule

2-4 Decoder
1 module decoder_2to4_gates (x,y,f0,f1,f2,f3);
2 input x,y;
3 output f0,f1,f2,f3;
4
5 wire n1,n2;
6
7 not i1 (n1,x);
8 not i2 (n2,y);
9 and a1 (f0,n1,n2);
10 and a2 (f1,n1,y);
11 and a3 (f2,x,n2);
12 and a4 (f3,x,y);
13
14 endmodule

4:2 Decoder
1 module encoder_4to2_gates (i0,i1,i2,i3,y);
2 input i0,i1,i2,i3;
3 output [1:0] y;
4
5 or o1 (y[0],i1,i3);
6 or o2 (y[1],i2,i3);
7
8 endmodule

Verilog

Binary-->Excess 3
module Convert_behav (BCD, Excess_3);
input [4: 1] BCD;
output [4: 1] Excess_3;
reg [4: 1] Excess_3;

always @ (BCD) Excess_3 = BCD + 4'b0011;
endmodule

// Verilog 2001, 2005

module Convert_behav (input [4: 1] BCD, output reg [4: 1] Excess_3); 2005
always @ (BCD) Excess_3 = BCD + 4'b0011;
endmodule

2:1 MUX
2:1 Mux



1 //-----------------------------------------------------
2 // Design Name : mux_2to1_gates
3 // File Name : mux_2to1_gates.v
4 // Function : 2:1 Mux using Gate Primitives
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module mux_2to1_gates(a,b,sel,y);
8 input a,b,sel;
9 output y;
10
11 wire sel,a_sel,b_sel;
12
13 not U_inv (inv_sel,sel);
14 and U_anda (asel,a,inv_sel),
15 U_andb (bsel,b,sel);
16 or U_or (y,asel,bsel);
17
18 endmodule


4:1 MUX
1 //-----------------------------------------------------
2 // Design Name : mux_4to1_gates
3 // File Name : mux_4to1_gates.v
4 // Function : 4:1 Mux Using Gates
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------

DE LAB

http://www.mediafire.com/?ej3ya2eajf4yrd1

Verilog experiments....

http://www.asic-world.com/examples/verilog/index.html


check out this link... It will be useful,..

OOPS SEM PRACTICAL QUESTIONS..... !!!

EVS

Output

Index

Bonafide

Student Information

Missed pages

Note:

Arrange the pages by yourself

ADC(5unit)

ADC-(5unit)

ADC

Part-b
1.DS-SPREAD SPECTRUM
2.FREQUENCY HOPING SPECTRUM
3.SPEECH FOR WIRELESS COMMUNICATION
4.PN CODE(m=3)
5.data communication circuit
6.error correction /detection
7.rake reciever
8.processing gain

Siddarath's blog

This is Our Siddharth's blog,have a look at this and support his blog!!!
http://rsiddharth.wordpress.com/

DPSD-Important questions

Part-A
1.VHDL and 6 keyword used.
2.JK flip-flop circuit & table equation
3.D flip-flop from SR flip-flop
4.verilog code for Boolean expression e=a+bc+b’d and
f=bc’+bcd+ab’c’
5.logic diagram for description module circuit(op y1,ip a,b,op y2); assign y1=a&b; or(y2,a,b) end module

Part-B
1.write the HDL code for 4*1 MUX.
2.draw the circuit and write the HDL code for 4-bit parallel adder.

More questions coming soon

Append

circle and cylinder

#include
#include
Class point
{
Protected:
Int xcor;
Int ycor;
Public:
Point(int x,int y)
{
Xcor=x;
Ycor=y;
}
Virtual void area()=0;
Virtual void volume()=0;
};
Class circle:public point
{
Protected:
Float radius;
Float area;
Float volume;
Public:
Void area(float rad)
{
Radius=rad;
Area=3.14*radius*radius;
Cout<}
Void volume(float rad)
{
Radius=rad;
Volume=(4/3)*3.14*radius*radius*radius;
Cout<}
};
Class cylinder:public circle
{
Protected:
Float height;
Float area1;
Float volume1;
Public:
Void area(float hei)
{
Height=hei;
Area1=2(circle::area)+2(3.14*circle::radius*height);
Cout<}
Void volume(float hei)
{
Height=hei;
Volume1=( circle::area)*height;
Cout<}
};
Void main()
{
Point p;
P.point(5,6);
Circle c1,c2;
C1.area(5.5);
C2.area(5.5);
Cylinder c3,c4;
C3.area(4.1);
C4.volume(4.1);
}

Hybrid inheritance

Remaining two questions i will mess/update soon

OOPS-2marks!

5.File manipulator(pg 543)

EVS-IMPORTANT QUESTIONS

http://www.megaupload.com/?d=LN88E0DC