Wednesday, October 20, 2010

Verilog questions

2to4 decoder
1to4 demux
4to1 mux
full adder
half adder
half subtractor
4 bit up/doen counter
siso
full subtractor
sipo
odd parity
even parity
xs3 to bcd
bcd to xs3
binary to gray
gray to binary
4input universal logic gates
octal to binary
8to 1 mux

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