Verilog

Binary-->Excess 3
module Convert_behav (BCD, Excess_3);
input [4: 1] BCD;
output [4: 1] Excess_3;
reg [4: 1] Excess_3;

always @ (BCD) Excess_3 = BCD + 4'b0011;
endmodule

// Verilog 2001, 2005

module Convert_behav (input [4: 1] BCD, output reg [4: 1] Excess_3); 2005
always @ (BCD) Excess_3 = BCD + 4'b0011;
endmodule

2:1 MUX
2:1 Mux



1 //-----------------------------------------------------
2 // Design Name : mux_2to1_gates
3 // File Name : mux_2to1_gates.v
4 // Function : 2:1 Mux using Gate Primitives
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module mux_2to1_gates(a,b,sel,y);
8 input a,b,sel;
9 output y;
10
11 wire sel,a_sel,b_sel;
12
13 not U_inv (inv_sel,sel);
14 and U_anda (asel,a,inv_sel),
15 U_andb (bsel,b,sel);
16 or U_or (y,asel,bsel);
17
18 endmodule


4:1 MUX
1 //-----------------------------------------------------
2 // Design Name : mux_4to1_gates
3 // File Name : mux_4to1_gates.v
4 // Function : 4:1 Mux Using Gates
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------